1. Field of the Invention
The present invention generally relates to a method and apparatus for manipulating a group of instances of a circuit design database, and more particularly relates to a method and apparatus for associating selected instances within the circuit design database, and for performing a group operation thereon.
2. Description of the Prior Art
The design process for all integrated circuits is composed of several discrete operations. Initially, the proposed functionality for a circuit is analyzed by one or more chip designers. These designers define the logical components of the circuit and their interactions by specifying the logic design using design capture tools. These design capture tools are commonly implemented in software executing on an engineering workstation, with well-known input devices being used to receive design information from the chip designer, and output devices, such as computer displays, being used to provide visual feedback of the design to the designer as it is being constructed. Such software is typically implemented as part of an electronic design automation (EDA) system. Specifically, the design entry operation involves generating a description of the logic design to be implemented on the circuit chip in an appropriate machine-readable form. Chip designers generally employ hierarchical design techniques to determine the appropriate selection and interconnection of logic and/or memory devices which will enable the chip to perform the desired function. These techniques involve describing the chip's functionality at various levels of abstraction, ranging from the most general function performed by the chip to the precise functions performed by each logic and/or memory element on the chip.
A common method for specifying the integrated circuit design is the use of hardware description languages. This method allows a circuit designer to specify the circuit at the register transfer level (also known as a “behavior description”). Using this method, the circuit is defined in small building blocks. The names of the building blocks are specified by the circuit designer. Thus, they usually are logical names with specific functional meaning.
Encoding the design in a hardware description language (HDL) is a major design entry technique used to specify modern integrated circuits. Hardware description languages are specifically developed to aid a designer in describing a circuit. These languages often contain specific functions and syntax to allow complex hardware structures to be described in a compact and efficient way.
Another common method for specifying the integrated circuit design is the use a schematic capture tool. A schematic capture tool allows the circuit designer to directly enter the schematics for the circuit design. Unlike a hardware description language, the resulting schematics often completely specify the logical and functional relationships among the components of the design.
It is useful to distinguish between those components of an integrated circuit design called cells, provided by a silicon chip vendor as primitive cells (i.e., leaf candidates), and the user-defined hierarchy blocks built upon them. One way is to speak of a “cell library” vs. a “design library” as two separate libraries, both of which are available to subsequent designs. Alternatively, at least initially, a design library contains a cell library. A cell library is a database containing detailed specifications on the characteristics of each logical component available for use in a design. Initial cell library contents are usually provided by the chip vendor. The components in the cell library are identified by the generic description of the component type. For example, the term “NAND” for a NAND gate is its type description and distinguishes this component from others such as OR gates, flip-flops, multiplexors, and so on. A two-input NAND gate might be of type 2NAND. When a 2NAND component is specified as part of a given circuit design, it is given an instance name, to distinguish it from all other 2NAND gates used in the circuit. The instance name typically includes the instance names of all parent instances by concatenation when defining the instance in the context of the chip.
The user-defined blocks can then be used to design larger blocks of greater complexity. The user-defined blocks are added to the design library, which grows from the additions of new design modules as the design evolves. The top level of the design hierarchy may be a single block that defines the entire design, and the bottom layer of the hierarchy may consist of leaf cells, the cells (i.e., the logical components) that were originally provided in the cell library. Note that the hierarchy is typically structured as a special kind of a graph called a tree. This resulting data structure is called a detailed (or gate-level) description of the logic design.
The generation of the detailed description is often accomplished by logic design synthesis software for HDL entry. The logic design synthesis software generates a gate-level description of user-defined input and output logic, and also creates new gate-level logic to implement user-defined logical functions. Constituent parts of new gate-level logic created during each pass through the logic design synthesis software are given computer-generated component and net names. Each time the logic design synthesis software is executed for the integrated circuit design, the component and net names which are generated by the software, and not explicitly defined by the user, may change, depending on whether new logic has been added to or deleted from the integrated circuit design. Typically, the logic design synthesis software is executed many times during the integrated circuit design process, because errors may be detected during the simulation and testing phases of the design cycle and then fixed in the behavioral description.
The output of the design capture and synthesis tools is a logic design database which completely specifies the logical and functional relationships among the components of the design. Once the design has been converted into this form, it may be optimized by sending the logic design database to a logic optimizer tool implemented in software. The logic optimizer may remove logic from the design that is unnecessary or otherwise improve the overall efficiency of the design. It is noted, however, that this action typically affects the component and net names generated by the logic synthesis tool.
It is also necessary to verify that the logic definition is correct and that the integrated circuit implements the function expected by the circuit designer. This verification is currently achieved by estimated timing and simulation software tools. The design undergoes design verification analysis in order to detect flaws in the design. The design is also analyzed by simulating a logic model of the design to assess the functionality of the design. If errors are found or the resulting functionality is unacceptable, the designer modifies the behavior description as needed. These design iterations help to ensure that the design satisfies its requirements. As a result of each revision to the design, the logic design synthesis-generated instance and net names may completely change. Further, the changes made by the logic optimizer may not be precisely known. Thus, the EDA tools downstream in the design process from the logic design synthesis software must be re-executed on the entire design.
After timing verification and functional simulation has been completed on the design, placement and routing of the design's components is performed. These steps involve assigning components of the design to locations on the integrated circuit chip and interconnecting the components to form nets. This may be accomplished using automated place and route tools.
Because automatic placement tools may not yield an optimal design solution, particularly for high performance designs that have strict timing and physical requirements, circuit designers often manually place critical circuit objects (e.g. cells or regions) within the boundary of the integrated circuit. This may be accomplished by using a placement directive tool (also known as a floorplanning tool), typically implemented in software. This floorplanning tool may include a graphical terminal that provides the circuit designer with visual information pertaining to the circuit design. This information is typically contained in several different windows.
A floor planning window may display a graphical representation of, for example, the die area of an integrated circuit, the placed objects and connectivity information. Similarly, a placed physical window may display the alphanumeric names of all placed cells and hierarchical regions. An un-placed physical window may display the alphanumeric names of all un-placed cells and hierarchical regions. A logic window may display a hierarchical tree graph of the circuit design.
During the placement process, the circuit designer may select the name of a desired object from the un-placed physical window displaying the un-placed objects. After this selection, the floorplanning tool may retrieve the physical representation of the selected object, and the circuit designer may use the cursor to position the physical representation of the selected object within the floor planning window. The floorplanning tool may then move the alphanumeric instance name of the selected object from the un-placed physical window to the placed physical window to indicate the placement thereof.
To edit the placement of desired objects, the circuit designer may select the desired representation of the object from the floor planning window using a pointing device. The circuit designer may, for example, draw a rectangle around the desired objects to affect the selection. After selection, the circuit designer may instruct the floorplanning tool to perform a desired editing function on the selected objects.
Some floorplanning tools allow the circuit designer to select a desired level of hierarchy or region as the current working environment, or “context”. When the context is set, all of the objects existing at the next lower level in the circuit design hierarchy are displayed in one of the physical windows, thus making them available for placement or editing. These objects are called children objects of the selected context, and may include other hierarchical objects, including regions and/or cells. Thus, a context may include a mixture of regions and cells.
In this environment, circuit designers may perform preliminary placement by first placing selected regions. In some floorplanning tools, the outer boundary of the regions is appropriately sized to accommodate all underlying objects, even though all of the objects may not yet be placed. The circuit designer then may rely on an automated placement tool to subsequently place the underlying objects within the boundary of the region. If more detailed placement is required because of timing, physical or other constraints, selected lower level regions or cells may be manually placed by the circuit designer.
These prior art floorplanning tools suffer from a number of limitations, some of which are described below. First, while some floorplanning tools may allow some editing operations to be performed on user-defined groups of objects, the circuit designer typically must select the objects using a pointing device within the floorplanning window (for example, selecting all objects within a selected area in the floorplanning window). The prior art floorplanning tools typically do not allow groups of instances to be defined as a group prior to entering the floorplanning tool. This provides a major limitation since many group operations are performed on groups of objects that may not be readily identifiable by the circuit designer from within the floorplanning tool.
In addition, when a context is loaded in some prior art floorplanning tools, the children cells may appear as a pseudo random list of names in a physical window. Since large contexts often contain thousands of regions and/or cells, the physical window may provide little utility during the placement process. The circuit designer simply must scroll through the often lengthy list of instances in an attempt to identify the desired objects for placement. It is often more efficient for the circuit designer to determine an instance name by cross-referencing an external listing so that the name can be entered manually prior to placement.
Thus, to place a desired group of objects in a typical prior art floorplanning tool, the circuit designer must execute a series of time-consuming steps. For example, to place a series of buffers that drive a vectored bus, the circuit designer must typically find and select each instance name associated with each bit in the vectored bus from a physical window. In many cases, the instance names do not indicate a correspondence to the vectored bus, and thus the circuit designer must locate each instance separately, either by referring to an external listing or by scrolling through an often lengthy list of cells in the un-placed physical window. Finally, the circuit designer must sequentially place and align each instance relative to the previously placed instances. Largely because of this tedious process, circuit designers often decide to not perform manual placement, if at all possible.